1. Field of the Invention
The present invention generally relates to nonvolatile ferroelectric memory device, and more particularly, to a nonvolatile ferroelectric memory device having a new signal line arrangement structure. The present invention effectively arranges signal lines for driving cell arrays to reduce delay of signals, and forms the signal lines of drivers above the cell array layer to decrease layout area of chip.
2. Description of the Background Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has attracted considerable attention as next generation memory device because it has the same data processing speed as a DRAM and conserves data even after the power is turned off.
The FeRAM includes capacitors similar to the DRAM, but the capacitors are made of a ferroelectric substance. The ferroelectric substance has the characteristic of a high residual polarization that data is not removed even after eliminating an electric field applied thereto.
FIG. 1 is a characteristic curve illustrating a hysteresis loop of a general ferroelectric substance.
As shown in FIG. 1, a polarization induced by an electric field remains at a certain portion (‘d’ or ‘a’ state) due to existence of the residual (or spontaneous) polarization even after the electric field is cleared.
For using the ferroelectric substance, these ‘d’ and ‘a’ states may be matched to binary values of ‘1’ and ‘0’.
FIG. 2 is a structural diagram illustrating a unit cell of the FRAM device.
As shown in FIG. 2, the unit cell of the conventional FRAM is provided with a bitline B/L arranged in one direction and a wordline W/L arranged in another direction vertical to the bitline B/L. A plateline P/L is arranged parallel to the wordline and spaced at a predetermined interval. The unit cell is also provided with a NMOS transistor having a gate connected to an adjacent wordline W/L and a source connected to an adjacent bitline B/L, and a ferroelectric capacitor FC1 connected between the drain terminal of the transistor T1 and the plateline P/L.
The data input/output operation of the conventional FRAM is now described as follows.
FIGS. 3a is a timing diagram illustrating a write mode of the FRAM while FIG. 3b is a timing diagram illustrating a read mode of the FRAM.
Referring to FIG. 3a, when an externally applied chip enable signal CSBPAD and a write enable signal WEBPAD transits from a high level to a low level, the array is enabled to start a write mode.
Thereafter, when an address is decoded in a write mode, a corresponding wordline transits from the low level to the high level, thereby selecting the cell.
During the wordline W/L maintains the high level, a ‘high’ signal of a predetermined interval and a ‘low’ signal of a predetermined interval are applied to the plateline P/L. In order to write binary logic values ‘1’ or ‘0’ in the selected cell, ‘high’ or ‘low’ signals synchronized to the write enable signal WEBPAD are applied to a corresponding bitline B/L.
As shown in the following Table 1, during a ‘high’ signal is applied to the wordline W/L, if a ‘high’ signal is applied to the bitline B/L and a ‘low’ signal is applied to the plateline P/L, a logic value ‘1’ is written in the ferroelectric capacitor FC1. If the ‘low’ signal is applied to the bitline B/L and the ‘high’ signal is applied to the plateline P/L, a logic value ‘0’ is written in the ferroelectric capacitor FC1.
TABLE 1P/LW/L: HHLB/LHX1L0X
Referring to FIG. 3B, If the externally applied chip enable signal CSBPAD is activated from the high level to the low level, all of the bitlines become equipotential to the low level by an equalizer signal before the corresponding wordline is selected.
Then, each bitline becomes inactive. A corresponding wordline according to the decoded address transits from the low level to the high level to select a cell.
The ‘high’ signal is applied to the plateline of the selected cell, to destroy a data Qs corresponding to a logic value ‘1’ stored in the ferroelectric memory cell. If a logic value ‘0’ is stored in the ferroelectric memory cell, its corresponding data Qns is not destroyed.
The destroyed data or the non-destroyed data are outputted to bitlines according to the above-described hysteresis loop characteristics, so that a sense amplifier can sense logic values ‘1’ or ‘0’.
AS shown in the hysteresis loop of FIG. 1, the state moves from ‘d’ to ‘f’ when the data is destroyed, while the state moves from ‘a’ to ‘f’ when the data is not destroyed.
As a result, if the sense amplifier is enabled after a set time has elapsed, the logic value ‘1’ is output in case the data is destroyed, while the logic value ‘0’ is output in case the data is not destroyed.
After the sense amplifier amplifies the data, the data should be recovered into the original data.
Accordingly, the plateline P/L becomes inactive and the corresponding wordline W/L is active, to recover the data.
In order to embody high integration of memory using the above-described FeRAM, it is important to effectively arrange cell arrays, peripheral controls and relevant circuits.
In general, the same control blocks are repeatedly used for controlling the cell arrays. The repeated use of the control blocks causes a problem in layout of chips for high integration.